2 * Copyright (c) 2014, Hewlett-Packard Development Company, LP.
3 * The license and distribution terms for this file are placed in LICENSE.txt.
6 * Syntax: X(<PAPI event name>, <event description>)
7 * Comment out some of the events to profile only required counters.
8 * Unfortunately many of them are not supported in Ivy Bridge Family 6 (as of PAPI 5.3),
9 * so we have to comment out most of them. Check papi_avail.
11 // see papiStdEventDefs.h
12 X(PAPI_L1_DCM, "Level 1 data cache misses")
13 X(PAPI_L1_ICM, "Level 1 instruction cache misses")
14 X(PAPI_L2_DCM, "Level 2 data cache misses")
15 X(PAPI_L2_ICM, "Level 2 instruction cache misses")
16 /* Ivy Bridge Family 6 not supported even in 5.3
17 X(PAPI_L3_DCM, "Level 3 data cache misses")
18 X(PAPI_L3_ICM, "Level 3 instruction cache misses")
20 X(PAPI_L1_TCM, "Level 1 total cache misses")
21 X(PAPI_L2_TCM, "Level 2 total cache misses")
22 X(PAPI_L3_TCM, "Level 3 total cache misses")
23 /* Ivy Bridge Family 6 not supported even in 5.3
24 X(PAPI_CA_SNP, "Snoops")
25 X(PAPI_CA_SHR, "Request for shared cache line (SMP)")
26 X(PAPI_CA_CLN, "Request for clean cache line (SMP)")
27 X(PAPI_CA_INV, "Request for cache line Invalidation (SMP)")
28 X(PAPI_CA_ITV, "Request for cache line Intervention (SMP)")
29 X(PAPI_L3_LDM, "Level 3 load misses")
30 X(PAPI_L3_STM, "Level 3 store misses")
31 X(PAPI_BRU_IDL, "Cycles branch units are idle")
32 X(PAPI_FXU_IDL, "Cycles integer units are idle")
33 X(PAPI_FPU_IDL, "Cycles floating point units are idle")
34 X(PAPI_LSU_IDL, "Cycles load/store units are idle")
36 X(PAPI_TLB_DM, "Data translation lookaside buffer misses")
37 X(PAPI_TLB_IM, "Instr translation lookaside buffer misses")
38 /* Ivy Bridge Family 6 not supported even in 5.3
39 X(PAPI_TLB_TL, "Total translation lookaside buffer misses")
41 /* papi_avail says these are supported, but seems like it doesn't work?
42 X(PAPI_L1_LDM, "Level 1 load misses")
43 X(PAPI_L1_STM, "Level 1 store misses")
45 /* Ivy Bridge Family 6 not supported even in 5.3
46 X(PAPI_L2_LDM, "Level 2 load misses")
48 /* papi_avail says these are supported, but seems like it doesn't work?
49 X(PAPI_L2_STM, "Level 2 store misses")
51 /* Ivy Bridge Family 6 not supported even in 5.3
52 X(PAPI_BTAC_M, "BTAC miss")
53 X(PAPI_PRF_DM, "Prefetch data instruction caused a miss")
54 X(PAPI_L3_DCH, "Level 3 Data Cache Hit")
55 X(PAPI_TLB_SD, "Xlation lookaside buffer shootdowns (SMP)")
56 X(PAPI_CSR_FAL, "Failed store conditional instructions")
57 X(PAPI_CSR_SUC, "Successful store conditional instructions")
58 X(PAPI_CSR_TOT, "Total store conditional instructions")
59 X(PAPI_MEM_SCY, "Cycles Stalled Waiting for Memory Access")
60 X(PAPI_MEM_RCY, "Cycles Stalled Waiting for Memory Read")
61 X(PAPI_MEM_WCY, "Cycles Stalled Waiting for Memory Write")
62 X(PAPI_STL_ICY, "Cycles with No Instruction Issue")
63 X(PAPI_FUL_ICY, "Cycles with Maximum Instruction Issue")
64 X(PAPI_STL_CCY, "Cycles with No Instruction Completion")
65 X(PAPI_FUL_CCY, "Cycles with Maximum Instruction Completion")
66 X(PAPI_HW_INT, "Hardware interrupts")
68 /* Some of these are supported, but we don't need.
69 X(PAPI_BR_UCN, "Unconditional branch instructions executed")
70 X(PAPI_BR_CN, "Conditional branch instructions executed")
71 X(PAPI_BR_TKN, "Conditional branch instructions taken")
72 X(PAPI_BR_NTK, "Conditional branch instructions not taken")
73 X(PAPI_BR_MSP, "Conditional branch instructions mispred")
74 X(PAPI_BR_PRC, "Conditional branch instructions corr. pred")
75 X(PAPI_FMA_INS, "FMA instructions completed")
76 X(PAPI_TOT_IIS, "Total instructions issued")
77 X(PAPI_TOT_INS, "Total instructions executed")
78 X(PAPI_INT_INS, "Integer instructions executed")
79 X(PAPI_FP_INS, "Floating point instructions executed")
80 X(PAPI_LD_INS, "Load instructions executed")
81 X(PAPI_SR_INS, "Store instructions executed")
82 X(PAPI_BR_INS, "Total branch instructions executed")
83 X(PAPI_VEC_INS, "Vector/SIMD instructions executed (could include integer)")
84 X(PAPI_RES_STL, "Cycles processor is stalled on resource")
85 X(PAPI_FP_STAL, "Cycles any FP units are stalled")
86 X(PAPI_TOT_CYC, "Total cycles executed")
87 X(PAPI_LST_INS, "Total load/store inst. executed")
88 X(PAPI_SYC_INS, "Sync. inst. executed")
89 X(PAPI_L1_DCH, "L1 D Cache Hit")
90 X(PAPI_L2_DCH, "L2 D Cache Hit")
91 X(PAPI_L1_DCA, "L1 D Cache Access")
92 X(PAPI_L2_DCA, "L2 D Cache Access")
93 X(PAPI_L3_DCA, "L3 D Cache Access")
94 X(PAPI_L1_DCR, "L1 D Cache Read")
95 X(PAPI_L2_DCR, "L2 D Cache Read")
96 X(PAPI_L3_DCR, "L3 D Cache Read")
97 X(PAPI_L1_DCW, "L1 D Cache Write")
98 X(PAPI_L2_DCW, "L2 D Cache Write")
99 X(PAPI_L3_DCW, "L3 D Cache Write")
100 X(PAPI_L1_ICH, "L1 instruction cache hits")
101 X(PAPI_L2_ICH, "L2 instruction cache hits")
102 X(PAPI_L3_ICH, "L3 instruction cache hits")
103 X(PAPI_L1_ICA, "L1 instruction cache accesses")
104 X(PAPI_L2_ICA, "L2 instruction cache accesses")
105 X(PAPI_L3_ICA, "L3 instruction cache accesses")
106 X(PAPI_L1_ICR, "L1 instruction cache reads")
107 X(PAPI_L2_ICR, "L2 instruction cache reads")
108 X(PAPI_L3_ICR, "L3 instruction cache reads")
109 X(PAPI_L1_ICW, "L1 instruction cache writes")
110 X(PAPI_L2_ICW, "L2 instruction cache writes")
111 X(PAPI_L3_ICW, "L3 instruction cache writes")
112 X(PAPI_L1_TCH, "L1 total cache hits")
113 X(PAPI_L2_TCH, "L2 total cache hits")
114 X(PAPI_L3_TCH, "L3 total cache hits")
115 X(PAPI_L1_TCA, "L1 total cache accesses")
116 X(PAPI_L2_TCA, "L2 total cache accesses")
117 X(PAPI_L3_TCA, "L3 total cache accesses")
118 X(PAPI_L1_TCR, "L1 total cache reads")
119 X(PAPI_L2_TCR, "L2 total cache reads")
120 X(PAPI_L3_TCR, "L3 total cache reads")
121 X(PAPI_L1_TCW, "L1 total cache writes")
122 X(PAPI_L2_TCW, "L2 total cache writes")
123 X(PAPI_L3_TCW, "L3 total cache writes")
124 X(PAPI_FML_INS, "FM ins")
125 X(PAPI_FAD_INS, "FA ins")
126 X(PAPI_FDV_INS, "FD ins")
127 X(PAPI_FSQ_INS, "FSq ins")
128 X(PAPI_FNV_INS, "Finv ins")
129 X(PAPI_FP_OPS, "Floating point operations executed")
130 X(PAPI_SP_OPS, " Floating point operations executed; optimized to count scaled single precision vector operations")
131 X(PAPI_DP_OPS, " Floating point operations executed; optimized to count scaled double precision vector operations")
132 X(PAPI_VEC_SP, " Single precision vector/SIMD instructions")
133 X(PAPI_VEC_DP, " Double precision vector/SIMD instructions")
134 X(PAPI_REF_CYC, " Reference clock cycles")
1.8.10 
